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 Multiprocessor System-on-Chip: Hardware Design and Tool Integration


Название: Multiprocessor System-on-Chip: Hardware Design and Tool Integration
Издательство: Sрringer
Автор: Michael Hübner, Jürgen Becker
Год: 2010
Количество страниц: 300
Формат: PDF
Размер: 4,5 mb
Язык: English

The purpose of this book is to evaluate strategies for future system design in multiprocessor system-on-chip (MPSoC) architectures. Both hardware design and integration of new development tools will be discussed. Novel trends in MPSoC design, combined with reconfigurable architectures are a main topic of concern. The main emphasis is on architectures, design-flow, tool-development, applications and system design.
Improving future electronic system performance can only be achieved by exploiting parallelism on all system levels. Multicore architectures offer a better performance/Watt ratio than single core architectures with similar performance. Combining multicore and coprocessor technology promises extreme computing power for highly CPU-time-consuming applications. FPGA-based accelerators not only offer the opportunity to speed up an application by implementing their compute-intensive kernels into hardware, but also to adapt to the dynamical behavior of an application. This book describes strategies for future system design in multiprocessor system-on-chip (MPSoC) architectures. Both hardware design and integration of new development tools are discussed. Novel trends in MPSoC design, combined with reconfigurable architectures are a main topic of concern. The main emphasis is on architectures, design-flow, tool-development, applications and system design. This book deals with key issues such as on-chip communication architectures, integration of reconfigurable hardware, and physical design of multiprocessor systems.
•Provides a state-of-the-art overview of system design using MPSoC architectures;
•Describes current trends in on-chip communication architectures;
•Offers extensive coverage of system design integrating MPSoC architectures with reconfigurable hardware;
•Includes coverage of challenges in physical design for multi- and manycore hardware architectures.

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